SH7052 Datasheet, PDF (128/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

UBARL:
Bit:
Initial value:
R/W:
15
UBA15
0
R/W
14
UBA14
0
R/W
13
UBA13
0
R/W
12
UBA12
0
R/W
11
UBA11
0
R/W
10
UBA10
0
R/W
9
UBA9
0
R/W
8
UBA8
0
R/W
Bit:
Initial value:
R/W:
7
UBA7
0
R/W
6
UBA6
0
R/W
5
UBA5
0
R/W
4
UBA4
0
R/W
3
UBA3
0
R/W
2
UBA2
0
R/W
1
UBA1
0
R/W
0
UBA0
0
R/W
The user break address register (UBAR) consists of user break address register H (UBARH) and
user break address register L (UBARL). Both are 16-bit readable/writable registers. UBARH
stores the upper bits (bits 31 to 16) of the address of the break condition, while UBARL stores the
lower bits (bits 15 to 0). UBARH and UBARL are initialized to H'0000 by a power-on reset and in
module standby mode. They are not initialized in software standby mode.
• UBARH Bits 15 to 0—User Break Address 31 to 16 (UBA31 to UBA16): These bits store the
upper bit values (bits 31 to 16) of the address of the break condition.
• UBARL Bits 15 to 0—User Break Address 15 to 0 (UBA15 to UBA0): These bits store the
lower bit values (bits 15 to 0) of the address of the break condition.
7.2.2 User Break Address Mask Register (UBAMR)
UBAMRH:
Bit: 15
14
13
12
11
10
9
8
UBM31 UBM30 UBM29 UBM28 UBM27 UBM26 UBM25 UBM24
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
UBM23 UBM22 UBM21 UBM20 UBM19 UBM18 UBM17 UBM16
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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