SH7052 Datasheet, PDF (182/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 9.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits (cont)
DMAC
Transfer
Request
RS4 RS3 RS2 RS1 RS0 Source
DMAC Transfer
Request Signal
Transfer
Source
Transfer
Destination Bus Mode
1
0
0
0
1
ATU-II
ICI0A (ICR0A input Don’t care* Don’t care* Burst/cycle-
capture generation)
steal
1
0
ATU-II
ICI0B (ICR0B input Don’t care* Don’t care* Burst/cycle-
capture generation)
steal
1 ATU-II ICI0C (ICR0C input Don’t care* Don’t care* Burst/cycle-
capture generation)
steal
1
0
0
ATU-II
ICI0D (ICR0D input Don’t care* Don’t care* Burst/cycle-
capture generation)
steal
1
ATU-II CMI6A (CYLR6A
Don’t care* Don’t care* Burst/cycle-
compare-match
steal
generation)
1
0
ATU-II CMI6B (CYLR6B
Don’t care* Don’t care* Burst/cycle-
compare-match
steal
generation)
1
ATU-II
CMI6C (CYLR6C
Don’t care* Don’t care* Burst/cycle-
compare-match
steal
generation)
1
0
0
0
ATU-II
CMI6D (CYLR6D
Don’t care* Don’t care* Burst/cycle-
compare-match
steal
generation)
1
ATU-II CMI7A (CYLR7A
Don’t care* Don’t care* Burst/cycle-
compare-match
steal
generation)
1
0
ATU-II CMI7B (CYLR7B
Don’t care* Don’t care* Burst/cycle-
compare-match
steal
generation)
1
ATU-II
CMI7C (CYLR7C
Don’t care* Don’t care* Burst/cycle-
compare-match
steal
generation)
1
0
0
ATU-II
CMI7D (CYLR7D
Don’t care* Don’t care* Burst/cycle-
compare-match
steal
generation)
Legend:
SCI0, SCI1, SCI2, SCI3, SCI4:
Serial communication interface channels 0 to 4
A/D0, A/D1:
A/D converter channels 0, 1
HCAN:
Hitachi controller area network channel 0
ATU-II:
Advanced timer unit
TDR0, TDR1, TDR2, TDR3, TDR4: SCI0 to SCI4 transmit data registers
RDR0, RDR1, RDR2, RDR3, RDR4: SCI0 to SCI4 receive data registers
ADDR0 to ADDR11:
A/D0 data registers
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