SH7619 Datasheet, PDF (98/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 3 Cache
3.4 Memory-Mapped Cache
To allow software management of the cache, cache contents can be read from or written to by the
MOV instructions. The address array is allocated to addresses H'F0000000 to H'F0FFFFFF, and
the data array to addresses H'F1000000 to H'F1FFFFFF. The address array and data array must be
accessed in longwords, and instruction fetches cannot be performed.
3.4.1 Address Array
The address array is allocated to H'F0000000 to H'F0FFFFFF. To access an address array, the 32-
bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array.
In the address field, specify the entry address for selecting the entry, W for selecting the way, A
for enabling or disabling the associative operation, and H'F0 for indicating address array access.
As for W, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3.
In the data field, specify the tag address, LRU bits, U bit, and V bit. Always clear the upper three
bits (bits 31 to 29) of the tag address to 0. Figure 3.4 shows the address and data formats. The
following three operations are available in the address array.
Address-Array Read: Read the tag address, LRU bits, U bit, and V bit for the entry that
corresponds to the entry address and way specified by the address field of the read instruction. In
reading, the associative operation is not performed, regardless of whether the associative bit (A
bit) specified in the address is 1 or 0.
Address-Array Write (Non-Associative Operation): Write the tag address, LRU bits, U bit, and
V bit, specified by the data field of the write instruction, to the entry that corresponds to the entry
address and way as specified by the address field of the write instruction. Ensure that the
associative bit (A bit) in the address field is set to 0. When writing to a cache line for which the U
bit = 1 and the V bit =1, write the contents of the cache line back to memory, then write the tag
address, LRU bits, U bit, and V bit specified by the data field of the write instruction. When 0 is
written to the V bit, 0 must also be written to the U bit for that entry.
Rev. 5.00 Mar. 15, 2007 Page 60 of 794
REJ09B0237-0500