SH7619 Datasheet, PDF (391/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states
is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
For details, see section 7, Bus State Controller (BSC).
DREQ Pin Sampling Timing: Figures 13.13, 13.14, 13.15, and 13.16 show the sample timing of
the DREQ input in each bus mode, respectively.
CKIO
Bus cycle
DREQ
(Rising edge)
DACK
(High-active)
CPU
CPU
1st acceptance
Non-sensitive period
DMAC
CPU
2nd acceptance
Acceptance started
Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
CKIO
Bus cycle
DREQ
(Overrun 0,
high-level)
DACK
(High-active)
CPU
CPU
1st acceptance
DMAC
Non-sensitive period
CPU
2nd acceptance
Acceptance started
CKIO
Bus cycle
DREQ
(Overrun 1,
high-level)
DACKn
(High-active)
CPU
CPU
1st acceptance
Non-sensitive period
DMAC
CPU
2nd acceptance
Non-sensitive period
Acceptance started
Figure 13.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
Rev. 5.00 Mar. 15, 2007 Page 353 of 794
REJ09B0237-0500