SH7619 Datasheet, PDF (19/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

19.5 Port E ................................................................................................................................ 578
19.5.1 Register Description ......................................................................................... 579
19.5.2 Port E Data Registers H and L (PEDRH and PEDRL) ..................................... 579
19.6 Usage Notes ...................................................................................................................... 581
Section 20 User Break Controller (UBC) ............................................................583
20.1 Features............................................................................................................................. 583
20.2 Register Descriptions........................................................................................................ 585
20.2.1 Break Address Register A (BARA) .................................................................. 585
20.2.2 Break Address Mask Register A (BAMRA)..................................................... 586
20.2.3 Break Bus Cycle Register A (BBRA)............................................................... 586
20.2.4 Break Address Register B (BARB) .................................................................. 587
20.2.5 Break Address Mask Register B (BAMRB) ..................................................... 588
20.2.6 Break Data Register B (BDRB) ........................................................................ 588
20.2.7 Break Data Mask Register B (BDMRB)........................................................... 589
20.2.8 Break Bus Cycle Register B (BBRB) ............................................................... 589
20.2.9 Break Control Register (BRCR) ....................................................................... 591
20.2.10 Execution Times Break Register (BETR)......................................................... 594
20.2.11 Branch Source Register (BRSR)....................................................................... 594
20.2.12 Branch Destination Register (BRDR)............................................................... 595
20.3 Operation .......................................................................................................................... 596
20.3.1 Flow of User Break Operation .......................................................................... 596
20.3.2 Break on Instruction Fetch Cycle...................................................................... 597
20.3.3 Break on Data Access Cycle............................................................................. 597
20.3.4 Sequential Break ............................................................................................... 598
20.3.5 Value of Saved Program Counter (PC)............................................................. 598
20.3.6 PC Trace ........................................................................................................... 599
20.3.7 Usage Examples................................................................................................ 600
20.3.8 Notes ................................................................................................................. 604
Section 21 User Debugging Interface (H-UDI) ...................................................605
21.1 Features............................................................................................................................. 605
21.2 Input/Output Pins.............................................................................................................. 606
21.3 Register Descriptions........................................................................................................ 607
21.3.1 Bypass Register (SDBPR) ................................................................................ 607
21.3.2 Instruction Register (SDIR) .............................................................................. 607
21.3.3 Boundary Scan Register (SDBSR) ................................................................... 608
21.3.4 ID Register (SDID)........................................................................................... 615
21.4 Operation .......................................................................................................................... 616
21.4.1 TAP Controller ................................................................................................. 616
Rev. 5.00 Mar. 15, 2007 Page xix of xxxviii