SH7619 Datasheet, PDF (11/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 6 Interrupt Controller (INTC) ...................................................................83
6.1 Features............................................................................................................................... 83
6.2 Input/Output Pins................................................................................................................ 85
6.3 Register Descriptions.......................................................................................................... 85
6.3.1 Interrupt Control Register 0 (ICR0).................................................................... 86
6.3.2 IRQ Control Register (IRQCR) .......................................................................... 87
6.3.3 IRQ Status register (IRQSR) .............................................................................. 90
6.3.4 Interrupt Priority Registers A to G (IPRA to IPRG)........................................... 95
6.4 Interrupt Sources................................................................................................................. 97
6.4.1 External Interrupts .............................................................................................. 97
6.4.2 On-Chip Peripheral Module Interrupts ............................................................... 99
6.4.3 User Break Interrupt ........................................................................................... 99
6.4.4 H-UDI Interrupt .................................................................................................. 99
6.5 Interrupt Exception Handling Vector Table...................................................................... 100
6.6 Interrupt Operation ........................................................................................................... 102
6.6.1 Interrupt Sequence ............................................................................................ 102
6.6.2 Stack after Interrupt Exception Handling ......................................................... 104
6.7 Interrupt Response Time................................................................................................... 104
Section 7 Bus State Controller (BSC)..................................................................107
7.1 Features............................................................................................................................. 107
7.2 Input/Output Pins.............................................................................................................. 110
7.3 Area Overview.................................................................................................................. 111
7.3.1 Area Division.................................................................................................... 111
7.3.2 Shadow Area..................................................................................................... 112
7.3.3 Address Map ..................................................................................................... 112
7.3.4 Area 0 Memory Type and Memory Bus Width ................................................ 114
7.3.5 Data Alignment................................................................................................. 114
7.4 Register Descriptions........................................................................................................ 115
7.4.1 Common Control Register (CMNCR) .............................................................. 116
7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5B, 6B) ............... 117
7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B) ................ 122
7.4.4 SDRAM Control Register (SDCR)................................................................... 138
7.4.5 Refresh Timer Control/Status Register (RTCSR)............................................. 139
7.4.6 Refresh Timer Counter (RTCNT)..................................................................... 141
7.4.7 Refresh Time Constant Register (RTCOR) ...................................................... 142
7.5 Operation .......................................................................................................................... 143
7.5.1 Endian/Access Size and Data Alignment.......................................................... 143
7.5.2 Normal Space Interface..................................................................................... 149
7.5.3 Access Wait Control ......................................................................................... 154
Rev. 5.00 Mar. 15, 2007 Page xi of xxxviii