SH7619 Datasheet, PDF (89/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 2 CPU
2.6 Processing States
2.6.1 State Transition
The CPU has the four processing states: reset, exception handling, program execution, and power-
down. Figure 2.4 shows the CPU state transition. Note that some products do not support the
manual reset function and the MRES pin.
RES = 0
in any state
RES = 1 and MRES = 0
in any state
Power-on reset state
Manual reset state
Reset state
Request for internal power-on reset
or internal manual reset by the WDT
Exception handling state
Request for NMI
or IRQ interrupt
Request for
exception handling
End of
exception handling
Program execution state
SLEEP instruction by
clearing SSBY bit
SLEEP instruction by
setting SSBY bit
Sleep mode
Software standby mode
Figure 2.4 CPU State Transition
Power-down mode
Rev. 5.00 Mar. 15, 2007 Page 51 of 794
REJ09B0237-0500