SH7619 Datasheet, PDF (362/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
Figure 13.1 shows the block diagram of the DMAC.
On-chip
memory
On-chip peripheral
module
DMA transfer
request signal
DMA transfer acknowledge signal
Interrupt controller
DEIn
Iteration
control
Register
control
Start-up
control
Request
priority
control
DMAC module
SARn
DARn
DMATCRn
CHCRn
DMAOR
DMASR0,
DMASR1
External
ROM
External
RAM
External
I/O (memory
mapped)
External
I/O (with
acknowledge-
ment)
DACK0, DACK1
TEND0, TEND1
DREQ0, DREQ1
Bus
interface
Bus state
controller
[Legend]
SARn:
DARn:
DMATCRn:
CHCRn:
DMAOR:
DMASR0,
DMASR1:
DEIn:
n:
DMA source address register
DMA destination address register
DMA transfer count register
DMA channel control register
DMA operation register
DMA extended resource selectors
DMA transfer-end interrupt request to the CPU
0, 1, 2, 3
Figure 13.1 Block Diagram of DMAC
Rev. 5.00 Mar. 15, 2007 Page 324 of 794
REJ09B0237-0500