SH7619 Datasheet, PDF (699/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
Output voltage
Maximum amplitude:
Because of Tx100 output,
normally around 1.0 V
Maximum amplitude
Amplitude adjustment
by bits DnA (n = 2 to 0)
Maximum amplitude/2
Slope adjustment
by bits DnCMP (n = 1, 0)
Slope adjustment
by bits DnSL (n = A, B)
Time
Figure 22.10 Role of Each Bit Field (Example of Rising Waveform)
Slope is Controlled in Four Segments
• How to Use (Example)
Write to the SIM registers in the following sequence.
Step
Register to Value for
be Written Writing
Description
1
0
H'2100
Select Tx100 mode. (This operation can be omitted if
Tx100 full-duplex or Tx100 half-duplex mode has been
selected by auto-negotiation,)*
2
20
H'0000
Start register write mode setting.
3
20
H'0000
Register write mode setting (continued)
4
20
H'0400
Register write mode setting (continued)
5
20
H'0000
Register write mode setting (continued)
6
20
H'0400
Finish register write mode setting.
7
23
H'xxxx
Write the setting value. (The initial value of this register is
H'81C8. Change the setting as necessary.)
8
20
H'4416
Validate the setting value (always write this value).
9
20
H'0000
Terminate the register write mode (return to normal
mode).
Note:
The setting of this register is initialized during the auto-negotiation process or when the
PHY module is reset (including a system reset of the LSI). Accordingly, when waveform
adjustment is to be performed by this register, the above steps must be carried out every
time the register is initialized.
Rev. 5.00 Mar. 15, 2007 Page 661 of 794
REJ09B0237-0500