SH7619 Datasheet, PDF (709/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 23 PHY Interface (PHY-IF)
23.2.3 PHY-IF SMI Register 3 (PHYIFSMIR3)
PHYIFSMIR3 is a 16-bit readable/writeable register, which sets the initial value of SMI register 3
in the case of the module reset the on-chip PHY module.
The changes of this register are taken by the on-chip PHY module reset with co_resetb.
PHYIFSMIR2 is initialized by power-on-reset. It is also initialized as H'0000 in the standby mode.
Bit
Bit name
Initial
value R/W
15 to 0 co_reg3_oui_in[15-0] All 0 R/W
Description
The initial value of SMI register 3 (= PHY
identifier 2)[15-0]
23.2.4 PHY-IF Address Register (PHYIFADDRR)
PHYIFADDRR is a 16-bit readable/writeable register, which sets the PHY address of the on-chip
PHY module.
The changes of this register are taken by the on-chip PHY module reset with co_resetb.
PHYIFADDRR is initialized by power-on-reset. It is also initialized as H'0000 in the standby
mode.
Bit
Bit name
15 to 5 
Initial
value R/W
All 0 R
4 to 0 co_st_phyadd[4-0] All 0 R/W
Description
Reserved.
These bits are always read as 0. The write value
should always be 0.
The initial value of PHY address
Rev. 5.00 Mar. 15, 2007 Page 671 of 794
REJ09B0237-0500