SH7619 Datasheet, PDF (403/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 14 Compare Match Timer (CMT)
14.2.2 Compare Match Timer Control/Status Register (CMCSR)
CMCSR is a 16-bit register that indicates compare match generation, enables interrupts and selects
the counter input clock.
CMCSR is initialized to H'0000 by a power-on reset and a transition to standby mode.
Bit
Bit Name
15 to 8 
7
CMF
6
CMIE
5 to 2 
Initial
value
All 0
0
0
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)* Compare Match Flag
Indicates whether or not the values of CMCNT and
CMCOR match.
0: CMCNT and CMCOR values do not match
[Clearing condition]
When 0 is written to this bit
1: CMCNT and CMCOR values match
R/W Compare Match Interrupt Enable
Enables or disables compare match interrupt (CMI)
generation when CMCNT and CMCOR values match
(CMF=1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 5.00 Mar. 15, 2007 Page 365 of 794
REJ09B0237-0500