SH7619 Datasheet, PDF (642/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 20 User Break Controller (UBC)
20.3.8 Notes
1. The CPU reads from or writes to the UBC registers via the I bus. A desired break may not
occur until the instruction to rewrite the UBC registers are executed and the actual values are
reflected. In order to know the timing the UBC register is changed, read the last written
register. Instructions after then are valid for the newly written register value.
2. UBC cannot monitor access to the L bus and I bus in the same channel.
3. Note on specification of sequential break:
A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel
match occurs in another bus cycle in sequential break setting. Therefore, no break occurs even
if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is
set.
4. When user breaks and other exceptions occur by the same instruction, they are handled
according to the priority listed in table 5.1 of section 5, Exception Handling. When an
exception with a higher priority is generated, no user break occurs.
 A break before the execution of an instruction is accepted with a priority over other
exceptions.
 When a break after the execution of an instruction or a data access break occurs
simultaneously with a re-execution-type exception with a higher priority (including a break
before the execution of an instruction), the re-execution-type exception is accepted and the
condition match flag is not set (however, there is an exception as explained in 5. of section
20.3.8, Notes). When the exception source of the re-execution type is cleared by exception
handling and the same instruction is executed again and completed, the break is generated
again and the flag is set.
 When a break after the execution of an instruction or a data access break occurs
simultaneously with a completion-type exception with a higher priority (TRAPA), no break
occurs but the condition match flag is set.
5. Note on exception of 4. of section 20.3.8, Notes
When a break after the execution of an instruction or a data access break occurs during the
execution of the instruction in which a CPU address error is generated by data access, the CPU
address error has a priority over the break and occurs before the break. The condition match
flag is also set at this time.
6. Note when a break occurs in the delay slot
When a break before the execution of an instruction is set to the delay slot instruction of the
RTE instruction, the break does not occur before executing the branch destination of the RTE
instruction.
7. User breaks are disabled during USB module standby mode. Do not read from or write to the
UBC registers during USB module standby mode; the values are not guaranteed.
Rev. 5.00 Mar. 15, 2007 Page 604 of 794
REJ09B0237-0500