SH7619 Datasheet, PDF (15/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

12.4 Usage Notes ...................................................................................................................... 304
12.4.1 Usage Notes on SH-Ether EtherC/E-DMAC Status Register (EESR).............. 304
12.4.2 Usage Notes on SH-Ether Transmit-FIFO Underflow...................................... 313
Section 13 Direct Memory Access Controller (DMAC) .....................................323
13.1 Features............................................................................................................................. 323
13.2 Input/Output Pins.............................................................................................................. 325
13.3 Register Descriptions........................................................................................................ 326
13.3.1 DMA Source Address Registers 0 to 3 (SAR_0 to SAR_3) ............................. 327
13.3.2 DMA Destination Address Registers 0 to 3 (DAR_0 to DAR_3) .................... 327
13.3.3 DMA Transfer Count Registers 0 to 3 (DMATCR_0 to DMATCR_3) ........... 327
13.3.4 DMA Channel Control Registers 0 to 3 (CHCR_0 to CHCR_3)...................... 328
13.3.5 DMA Operation Register (DMAOR) ............................................................... 333
13.3.6 DMA Extended Resource Selectors 0 and 1 (DMARS0 and DMARS1) ......... 335
13.4 Operation .......................................................................................................................... 337
13.4.1 DMA Transfer Flow ......................................................................................... 337
13.4.2 DMA Transfer Requests ................................................................................... 339
13.4.3 Channel Priority................................................................................................ 341
13.4.4 DMA Transfer Types........................................................................................ 344
13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ....................... 353
13.5 Usage Notes ...................................................................................................................... 357
13.5.1 Notes on DACK Pin Output ............................................................................. 357
13.5.2 Notes On DREQ Sampling When DACK is Divided in External Access ........ 358
13.5.3 Other Notes ....................................................................................................... 361
Section 14 Compare Match Timer (CMT) ..........................................................363
14.1 Features............................................................................................................................. 363
14.2 Register Descriptions........................................................................................................ 364
14.2.1 Compare Match Timer Start Register (CMSTR) .............................................. 364
14.2.2 Compare Match Timer Control/Status Register (CMCSR) .............................. 365
14.2.3 Compare Match Counter (CMCNT) ................................................................. 366
14.2.4 Compare Match Constant Register (CMCOR) ................................................. 366
14.3 Operation .......................................................................................................................... 367
14.3.1 Interval Count Operation .................................................................................. 367
14.3.2 CMCNT Count Timing..................................................................................... 367
14.4 Interrupts........................................................................................................................... 368
14.4.1 Interrupt Sources............................................................................................... 368
14.4.2 Timing of Setting Compare Match Flag ........................................................... 368
14.4.3 Timing of Clearing Compare Match Flag......................................................... 368
14.5 Usage Notes ...................................................................................................................... 369
Rev. 5.00 Mar. 15, 2007 Page xv of xxxviii