SH7619 Datasheet, PDF (105/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 5 Exception Handling
Section 5 Exception Handling
5.1 Overview
5.1.1 Types of Exception Handling and Priority
Exception handling is started by four sources: resets, address errors, interrupts and instructions and
have the priority, as shown in table 5.1. When several exceptions are detected at once, they are
processed according to the priority.
Table 5.1 Types of Exceptions and Priority
Exception
Reset
Interrupt
Address error
Instruction
Address error
Interrupt
Exception Source
Power-on reset
H-UDI reset
User break (break before instruction execution)
CPU address error (instruction fetch)
General illegal instructions (undefined code)
Illegal slot instruction (undefined code placed immediately after a
delayed branch instruction*¹ or instruction that changes the PC
value*²)
Trap instruction (TRAPA instruction)
CPU address error (data access)
User break (break after instruction execution or operand break)
NMI
H-UDI
IRQ
On-chip
peripheral
modules
Watchdog timer (WDT)
Ether controller (EtherC and E-DMAC)
Compare match timer 0 and 1 (CMT0 and CMT1)
Serial communication interface with FIFO (SCIF0,
SCIF1, and SCIF2)
Host interface (HIF)
Priority
High
Low
Rev. 5.00 Mar. 15, 2007 Page 67 of 794
REJ09B0237-0500