SH7619 Datasheet, PDF (264/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 10 Power-Down Modes
10.3.2 Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in power-
down mode.
Initial
Bit
Bit Name Value R/W
Description
7
MSTP10 0
R/W
Module Stop Bit 10
When this bit is set to 1, the supply of the clock to
the H-UDI is halted.
0: H-UDI operates
1: Clock supply to H-UDI halted
6
MSTP9 0
R/W
Module Stop Bit 9
When this bit is set to 1, the supply of the clock to
the UBC is halted.
0: UBC operates
1: Clock supply to UBC halted
5
MSTP8 0
R/W
Module Stop Bit 8
When this bit is set to 1, the supply of the clock to
the DMAC is halted.
0: DMAC operates
1: Clock supply to DMAC halted
4, 3

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2
MSTP5 0
R/W
Module Stop Bit 5
When this bit is set to 1, the supply of the clock to
the cache memory is halted.
0: Cache memory operates
1: Clock supply to cache memory halted
1
MSTP4 0
R/W
Module Stop Bit 4
When this bit is set to 1, the supply of the clock to
the U memory is halted.
0: U memory operates
1: Clock supply to the U memory halted
Rev. 5.00 Mar. 15, 2007 Page 226 of 794
REJ09B0237-0500