SH7619 Datasheet, PDF (818/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Item
15.4.3 Synchronous Operation
Clock
Figure 15.13 Sample Flowchart
for Transmitting Serial Data
Figure 15.18 Sample Flowchart
for Transmitting/Receiving Serial
Data
Page Revision (See Manual for Details)
424 Amended
:
When only receiving, the clock signal outputs while the
RE bit of SCSCR is 1 and the number of data in receive
FIFO is less than the receive FIFO data trigger number.
In this case, 8 × (16 + 1) = 136 pulses of synchronous
clock are output. To perform reception of n characters
of data, select an external clock as the clock source. If
an internal clock should be used, set RE = 1 and TE =
1 and receive n characters of data simultaneously with
the transmission of n characters of dummy data.
426 Amended
430
Start of transmission
Read TDFE flag in SCFSR
[1] SCIF status check and transmit data
write:
No
TDFE = 1?
Yes
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR. Read the
TDFE and TEND flags while they are
1, then clear them to 0.
Write transmit data to SCFTDR
Read TDFE and TEND flags
in SCFSR while they are 1, then
clear them to 0
[1]
[2] Serial transmission continuation
procedeure:
To continue serial transmission, read
1 from the TDFE flag to confirm that
writing is possible, them write data to
Amended
Initialization
Start of transmission and reception
Read TDFE flag in SCFSR
No
TDFE = 1?
Yes
Write transmit data to SCFTDR
Read TDFE and TEND flags
[1]
in SCFSR while they are 1, then
clear them to 0
[1] SCIF status check and transmit data
write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR. Read the
TDFE and TEND flags while they are
1, then clear them to 0. The transition
of the TDFE flag from 0 to 1 can also
be identified by a TXI interrupt.
[2] Receive error handling:
Read the ORER flag in SCLSR to
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0. Reception cannot
be resumed while the ORER flag is
set to 1.
[3] SCIF status check and receive data
read:
18.1.6 Port C Control Register
H2, L1, and L2 (PCCRH2,
PCCRL1, and PCCRL2)
• PCCRL2
557
Amended
bit
Description
13
PC6 Mode
12
Select the function of pin PC6/MII_TXD2/CRS.
00: PC06 input/output (port)
01: MII_TXD2 output (EtherC)
10: Setting prohibited
11: CRS output (PHY)
Rev. 5.00 Mar. 15, 2007 Page 780 of 794
REJ09B0237-0500