SH7619 Datasheet, PDF (712/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 23 PHY Interface (PHY-IF)
5 The reset of the on-chip PHY
Before you reset the on-chip PHY module, please set the register sets of PHY-IF parts as you
need, except PHYIFCR. After that, set the co_resetb of PHYIFCR as zero, to make the on-chip
PHY reset state.
At this moment, you should set the other bits of PHYIFCR, which corresponds to the operating
mode of the on-chip PHY. Please adjust the waiting time with software-loop, etc., so that you
can keep the reset period is over 100 µs.
6. Release of the reset of the on-chip PHY.
Set only the co_resetb of PHYIFCR as "1", for releasing the reset state of the on-chip PHY.
After releasing the reset, adjust the waiting time with software loops, etc. as over 20 ms for
propagation of reset signal within the PHY.
7. Set up the on-chip PHY module with the MII management frame.
The procedures after this step are set up by the MII management frame like an external PHY
LSI on the market.
Please refer the section of PHY module about the each settings of it.
23.3.2 The Procedures of Set Up the External PHY LSI
In the case of utilizing the external PHY LSI, select the EtherC function of the pin function
controllers and then set up the internal registers of the PHY LSI with the MII management frame.
1. Activation of the external PHY LSI.
Select the EtherC functions with pin function controller.
• PCCRH = H'0155
• PCCRL1 = H'5555
• PCCRL2 = H'5555
2. Set up the external PHY LSI with the MII management frame.
Following procedures are set up by the MII management frame.
About the each settings of the PHY LSI that you utilize, please refer the documents of it.
Rev. 5.00 Mar. 15, 2007 Page 674 of 794
REJ09B0237-0500