SH7619 Datasheet, PDF (199/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Setting
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11
(32
bits)
00
00
(11 bits) (8 bits)
11
(32
bits)
01
00
(12 bits) (8 bits)
Output
Pins of Output
This Row
LSI
Address
Output
Column
Address
Pins of
SDRAM Function
Output
Pins of Output
This Row
LSI
Address
Output
Column
Address
Pins of
SDRAM
Function
A1
A9
A1
Unused
A1
A9
A1
Unused
A0
A8
A0
A0
A8
A0
Example of memory connection
Example of memory connection
One 64-Mbit product (512 kwords x 32 bits x 4 banks, 8-
bit column product)
One 128-Mbit product (1 Mword x 32 bits x 4 banks, 8-bit
column product)
Two 16-Mbit products (512 kwords x 16 bits x 2 banks, 8- Two 64-Mbit product (1 Mword x 16 bits x 4 banks, 8-bit
bit column product)
column product)
Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the
access mode.
2. Bank address specification
3. Applicable only to a 64-Mbit product
Table 7.13 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and
A3COL[1:0]) and Address Multiplex Output (2)
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11
(32
bits)
01
01
(12 bits) (9 bits)
Output
Pins of Output
This Row
LSI
Address
Output
Column
Address
A17 A26
A17
A16 A25
A16
A15
A24*²
A24*²
A14
A23*²
A23*²
Pins of
SDRAM
Function
Unused
A13 (BA1) Specifies
A12 (BA0) ^bank
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11
(32
bits)
01
10
(12 bits) (10 bits)
Output
Pins of
This
LSI
Output
Row
Address
Output
Column
Address
A17 A27
A17
A16 A26
A16
A15
A25*²
A25*²
A14
A24*²
A24*²
Pins of
SDRAM
Function
Unused
A13 (BA1) Specifies
A12 (BA0) ^bank
Rev. 5.00 Mar. 15, 2007 Page 161 of 794
REJ09B0237-0500