SH7619 Datasheet, PDF (474/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
15.7 Usage Notes
Note the following when using the SCIF.
1. SCFTDR Writing and TDFE Flag
The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data
bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit
trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After
TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written,
allowing efficient continuous transmission.
However, if the number of data bytes written in SCFTDR is equal to or less than the transmit
trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0.
TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit
trigger number of transmit data bytes.
The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO
data count register (SCFDR).
2. SCFRDR Reading and RDF Flag
The RDF flag in the serial status register (SCFSR) is set when the number of receive data bytes
in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive
trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After
RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing
efficient continuous reception.
However, if the number of data bytes in SCFRDR is equal to or greater than the trigger
number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be
cleared to 0 after being read as 1 after all the receive data has been read.
The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO
data count register (SCFDR).
3. Break Detection and Processing
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is
detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set
and the parity error flag (PER) may also be set. Note that, although transfer of receive data to
SCFRDR is halted in the break state, the SCIF receiver continues to operate.
Rev. 5.00 Mar. 15, 2007 Page 436 of 794
REJ09B0237-0500