SH7619 Datasheet, PDF (557/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W
Description
0
DTRG
0
R/W*¹ *² HIFDREQ Trigger
When 1 is written to this bit, the HIFDREQ pin is
asserted according to the setting of the DMD and
DPOL bits in HIFSCR. This bit is automatically cleared
to 0 in synchronization with negate of the HIFDREQ
pin.
Though this bit can be set to 1 by the on-chip CPU, it
cannot be cleared to 0.
To avoid conflict between clearing of this bit by negate
of the HIFDREQ pin and setting of this bit by the on-
chip CPU, make sure this bit is cleared to 0 before
setting this bit to 1 by the on-chip CPU.
Notes: 1. This bit cannot be accessed by an external device. It can be accessed only by the on-
chip CPU.
2. Writing 0 to this bit by the on-chip CPU is ignored.
17.4.11 HIF Bank Interrupt Control Register (HIFBICR)
HIFBICR is a 32-bit register that controls HIF bank interrupts. HIFBICR cannot be accessed by an
external device.
Bit
31 to 2
Initial
Bit Name Value
—
All 0
1
BIE
0
R/W
R*¹
R/W*¹
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Bank Interrupt Enable
Enables or disables a bank interrupt request (HIFBI)
issued to the on-chip CPU.
0: HIFBI disabled
1: HIFBI enabled
Rev. 5.00 Mar. 15, 2007 Page 519 of 794
REJ09B0237-0500