SH7619 Datasheet, PDF (663/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
22.4 PHY Management Control
The Management Control module includes 2 blocks:
• Serial Management Interface (SMI)
• Management Registers Set
22.4.1 Serial Management Interface (SMI)
The Serial Management Interface is used to control this PHY core and obtain its status. This
interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard. Non-
supported registers (7 to 15) will be read as hexadecimal "FFFF".
At the system level there are 2 signals, MDIO and MDC where MDIO is bi-directional open-drain
and MDC is the clock. In the core there is no notion of bi-directional signals so the MDIO signal
is implemented as 3 signals: CO_MDIO_DIR, CO_MDO and CO_MDI. The relationship among
these signals is made clear in Figure 22.3.
ENB
CO_MDIO_DIR
CO_MDIO
MDIO
CO_MDI
EtherC side
PHY module side
Inside of this LSI
Note: Drivers are in open-drain state
Figure 22.3 How to Derive MDIO Signal from Core Signals
The CO_MDC signal is an a-periodic clock provided by the station management controller
(SMC). The CO_MDI signal receives serial data (commands) from the controller SMC. The
CO_MDO sends serial data (status) to the SMC.
The minimum time between edges of the CO_MDC is 160 ns. There is no maximum time between
edges. The minimum cycle time (time between two consecutive rising or two consecutive falling
edges) is 400 ns. These modest timing requirements allow this interface to be easily driven by the
CPU.
Rev. 5.00 Mar. 15, 2007 Page 625 of 794
REJ09B0237-0500