SH7619 Datasheet, PDF (508/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
3
CD1A3 0
R/W Control Channel 1 Data Assigns 3 to 0
2
CD1A2 0
R/W Specify the position of control channel 1 data in a
1
CD1A1 0
R/W ^{receive or transmit frame as B'0000 (0) to B'1110 (14).}
0
CD1A0 0
R/W ^{1111: Setting prohibited}
• Transmit data for the control channel 1 data is
specified in the SITD1 bit in SITCR.
• Receive data for the control channel 1 data is stored
in the SIRD1 bit in SIRCR.
16.3.14 SPI Control Register (SPICR)
SPICR is a 16-bit readable/writable register that specifies the operating mode of the SPI.
Initial
Bit Bit Name Value R/W Description
15
SPIM
0
R/W SPI Mode
Selects the SIOF operating mode.
0: Operates as the SIOF.
1: The SIOF operates in master mode of the SPI.
14

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
13
CPHA
0
R/W SPI Clock Phase
Selects the SPI clock phase.
0: Samples data at the first edge of the SCK.
1: Samples data at the second edge of the SCK.
12
CPOL
0
R/W SPI Clock Polarity
Selects the SPI clock polarity.
0: The SCK is high-active, and goes low in the idle state.
1: The SCK is low-active, and goes high in the idle state.
Rev. 5.00 Mar. 15, 2007 Page 470 of 794
REJ09B0237-0500