SH7619 Datasheet, PDF (14/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

11.4.1 Transmission..................................................................................................... 253
11.4.2 Reception .......................................................................................................... 255
11.4.3 MII Frame Timing ............................................................................................ 256
11.4.4 Accessing MII Registers................................................................................... 258
11.4.5 Magic Packet Detection .................................................................................... 261
11.4.6 Operation by IPG Setting.................................................................................. 262
11.4.7 Flow Control..................................................................................................... 262
11.5 Connection to PHY-LSI.................................................................................................... 263
11.6 Usage Notes ...................................................................................................................... 264
Section 12 Ethernet Controller Direct Memory Access Controller
(E-DMAC)........................................................................................ 265
12.1 Features............................................................................................................................. 265
12.2 Register Descriptions........................................................................................................ 266
12.2.1 E-DMAC Mode Register (EDMR) ................................................................... 267
12.2.2 E-DMAC Transmit Request Register (EDTRR) .............................................. 268
12.2.3 E-DMAC Receive Request Register (EDRRR)................................................ 269
12.2.4 Transmit Descriptor List Address Register (TDLAR)...................................... 270
12.2.5 Receive Descriptor List Address Register (RDLAR) ....................................... 270
12.2.6 EtherC/E-DMAC Status Register (EESR)........................................................ 271
12.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)................... 276
12.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)............................. 279
12.2.9 Receive Missed-Frame Counter Register (RMFCR) ........................................ 281
12.2.10 Transmit FIFO Threshold Register (TFTR)...................................................... 282
12.2.11 FIFO Depth Register (FDR) ............................................................................. 283
12.2.12 Receiving Method Control Register (RMCR) .................................................. 284
12.2.13 E-DMAC Operation Control Register (EDOCR) ............................................. 285
12.2.14 Receiving-Buffer Write Address Register (RBWAR) ...................................... 286
12.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) ................................. 286
12.2.16 Transmission-Buffer Read Address Register (TBRAR)................................... 286
12.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) ............................ 287
12.2.18 Flow Control FIFO Threshold Register (FCFTR) ............................................ 287
12.2.19 Transmit Interrupt Register (TRIMD) .............................................................. 288
12.3 Operation .......................................................................................................................... 289
12.3.1 Descriptor List and Data Buffers ...................................................................... 289
12.3.2 Transmission..................................................................................................... 298
12.3.3 Reception .......................................................................................................... 300
12.3.4 Multi-Buffer Frame Transmit/Receive Processing ........................................... 302
Rev. 5.00 Mar. 15, 2007 Page xiv of xxxviii