SH7619 Datasheet, PDF (713/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 24 List of Registers
Section 24 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)
• Registers are listed from the lower allocation addresses.
• Reserved addresses are indicated by  in the register name column.
Do not access the reserved addresses.
• When registers consist of 16 or 32 bits, the addresses of the MSBs are given.
• Registers are classified according to functional modules.
• The numbers of Access Cycles are given.
2. Register bits
• Bit configurations of the registers are listed in the same order as the register addresses.
• Reserved bits are indicated by  in the bit name column.
• Space in the bit name field indicates that the entire register is allocated to either the counter or
data.
• For the registers of 16 or 32 bits, the MSB is listed first.
3. Register states in each operating mode
• Register states are listed in the same order as the register addresses.
• The register states shown here are for the basic operating modes. If there is a specific reset for
an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Rev. 5.00 Mar. 15, 2007 Page 675 of 794
REJ09B0237-0500