SH7619 Datasheet, PDF (424/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.7 Serial Status Register (SCFSR)
SCFSR is a 16-bit register. The upper 8 bits indicate the number of receives errors in the SCFRDR
data, and the lower 8 bits indicate the status flag indicating SCIF operating state.
The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND,
TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. SCFSR is
initialized to H'0060 by a power-on reset.
Initial
Bit
Bit Name value R/W Description
15
PER3
0
R
Number of Parity Errors
14
PER2
0
13
PER1
0
12
PER0
0
R
Indicate the number of data including a parity error in
R
the receive data stored in the receive FIFO data
register (SCFRDR). The value indicated by bits 15 to
R
12 represents the number of parity errors in SCFRDR.
When parity errors have occurred in all 16-byte
receive data in SCFRDR, PER3 to PER0 show 0.
11
FER3
0
R
Number of Framing Errors
10
FER2
0
9
FER1
0
8
FER0
0
R
Indicate the number of data including a framing error
R
in the receive data stored in SCFRDR. The value
indicated by bits 11 to 8 represents the number of
R
framing errors in SCFRDR. When framing errors have
occurred in all 16-byte receive data in SCFRDR,
FER3 to FER0 show 0.
Rev. 5.00 Mar. 15, 2007 Page 386 of 794
REJ09B0237-0500