SH7619 Datasheet, PDF (439/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.9 FIFO Control Register (SCFCR)
SCFCR is a 16-bit register that resets the number of data in the transmit and receive FIFO
registers, sets the trigger data number, and contains an enable bit for loop-back testing. SCFCR
can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset.
Bit
Bit Name
15 to 11 
10
RSTRG2
9
RSTRG1
8
RSTRG0
Initial
value
All 0
0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W RTS Output Active Trigger
R/W When the number of receive data in the receive FIFO
R/W
register (SCFRDR) becomes more than the number
shown below, the RTS signal is set to high.
These bits are available only in SCFCR_0 and
SCFCR_1. In SCFCR_2, these bits are reserved. The
initial value is 0 and the write value should always be 0.
000: 15
001: 1
010: 4
011: 6
100: 8
101: 10
110: 12
111: 14
Rev. 5.00 Mar. 15, 2007 Page 401 of 794
REJ09B0237-0500