SH7619 Datasheet, PDF (84/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 2 CPU
Instruction
Operation
Code
Execution
Cycles T Bit
DMULU.L
Rm,Rn Unsigned operation of
0011nnnnmmmm0101 2 to 5*

Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
DT Rn
Rn - 1 → Rn, if Rn = 0, 1 → 0100nnnn00010000 1
T, else 0 → T
Comparison
result
EXTS.B Rm,Rn
A byte in Rm is sign-
0110nnnnmmmm1110 1

extended → Rn
EXTS.W Rm,Rn
A word in Rm is sign-
0110nnnnmmmm1111 1

extended → Rn
EXTU.B Rm,Rn
A byte in Rm is zero-
0110nnnnmmmm1100 1

extended → Rn
EXTU.W Rm,Rn
A word in Rm is zero-
0110nnnnmmmm1101 1

extended → Rn
MAC.L @Rm+,@Rn+ Signed operation of (Rn) 0000nnnnmmmm1111 2 to 5*

× (Rm) + MAC → MAC,
32 × 32 + 64 → 64 bits
MAC.W @Rm+,@Rn+ Signed operation of (Rn) 0100nnnnmmmm1111 2 to 4*

× (Rm) + MAC → MAC,
16 × 16 + 64 → 64 bits
MUL.L Rm,Rn
Rn × Rm → MACL
32 × 32 → 32 bits
0000nnnnmmmm0111 2 to 5*

MULS.W Rm,Rn
Signed operation of Rn
0010nnnnmmmm1111 1 (3)*

× Rm → MAC
16 × 16 → 32 bits
MULU.W Rm,Rn
Unsigned operation of
0010nnnnmmmm1110 1 (3)*

Rn × Rm → MAC
16 × 16 → 32 bits
NEG Rm,Rn
0-Rm → Rn
0110nnnnmmmm1011 1

NEGC Rm,Rn
0-Rm-T → Rn,
Borrow → T
0110nnnnmmmm1010 1
Borrow
SUB Rm,Rn
Rn-Rm → Rn
0011nnnnmmmm1000 1

SUBC Rm,Rn
Rn-Rm–T → Rn,
Borrow → T
0011nnnnmmmm1010 1
Borrow
Rev. 5.00 Mar. 15, 2007 Page 46 of 794
REJ09B0237-0500