SH7619 Datasheet, PDF (288/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 11 Ethernet Controller (EtherC)
11.3.16 Too-Long Frame Receive Counter Register (TLFRCR)
TLFRCR is a 32-bit counter that indicates the number of frames received with a length exceeding
the value specified by the receive frame length register (RFLR). When the value in this register
reaches H'FFFFFFFF, the count is halted. TLFRCR is not incremented when a frame containing
residual bits is received. In this case, the reception of the frame is indicated in the residual-bit
frame counter register (RFCR). The counter value is cleared to 0 by a write to this register with
any value.
Bit Bit Name
31 to 0 TLFC31 to
TLFC0
Initial
Value
All 0
R/W Description
R/W Too-Long Frame Receive Count
These bits indicate the count of frames received with
a length exceeding the value in RFLR.
11.3.17 Residual-Bit Frame Counter Register (RFCR)
RFCR is a 32-bit counter that indicates the number of frames received containing residual bits
(less than an 8-bit unit). When the value in this register reaches H'FFFFFFFF, the count is halted.
The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name
31 to 0 RFC31 to
RFC0
Initial
Value
All 0
R/W Description
R/W Residual-Bit Frame Count
These bits indicate the count of frames received
containing residual bits.
11.3.18 Multicast Address Frame Counter Register (MAFCR)
MAFCR is a 32-bit counter that indicates the number of frames received with a specified multicast
address. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter
value is cleared to 0 by a write to this register with any value.
Bit Bit Name
31 to 0 MAFC31 to
MAFC0
Initial
Value
All 0
R/W Description
R/W Multicast Address Frame Count
These bits indicate the count of multicast frames
received.
Rev. 5.00 Mar. 15, 2007 Page 250 of 794
REJ09B0237-0500