SH7619 Datasheet, PDF (171/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
9

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
8
A3CL1 1
R/W CAS Latency for Area 3.
7
A3CL0 0
R/W Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: Reserved (setting prohibited)
6, 5

All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
TRWL1 0
R/W Wait Cycle Number for Precharge Start Wait
3
TRWL0 0
R/W Specify the number of minimum wait cycles inserted to
wait for the start of precharge in the following cases.
• From the issuing of the WRITA command by this LSI
to the start of the auto-precharge in the SDRAM.
The ACTV command for the same bank is issued
after issuing the WRITA command in non-bank active
mode.
To confirm how many cycles should be needed in the
SDRAM between receiving the WRITA command and
the auto-precharge start, refer to the data sheets for
each SDRAM. Set this bit so that the cycle number in
that data sheets should not exceed the cycle number
set by this bit.
• From the issuing of the WRIT command by this LSI to
the issuing of the PRE command.
A different row address in the same bank is accessed
in bank active mode.
00: 0 cycle (no wait cycle)
01: 1 cycle
10: 2 cycles
11: 3 cycles
Rev. 5.00 Mar. 15, 2007 Page 133 of 794
REJ09B0237-0500