SH7619 Datasheet, PDF (565/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
When the external DMAC is specified to detect the falling edge of the HIFDREQ signal, set DMD
= 1 and DPOL = 0. After writing 1 to the DTRG bit, a low pulse of 32 peripheral clock cycles is
generated at the HIFDREQ pin.
DTRG bit
DPOL bit
HIFDREQ
Asserted in synchronization
with the DTRG bit being set
by the on-chip CPU.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
After assert, negated when
tPCYC (peripheral clock cycle) × 32 cyc have elapsed.
Figure 17.10 HIFDREQ Timing (When DMD = 1 and DPOL = 0)
When the external DMAC is specified to detect the rising edge of the HIFDREQ signal, set DMD
= 1 and DPOL = 1. At the time the DPOL bit is set to 1, HIFDREQ becomes low. Then after
writing 1 to the DTRG bit, a low pulse of 32 peripheral clock cycles is generated at the HIFDREQ
pin.
DTRG bit
DPOL bit
Negated in synchronization
with the DPOL bit being set
by the on-chip CPU.
HIFDREQ
Asserted in synchronization
with the DTRG bit being set
by the on-chip CPU.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
After assert, negated when
tPCYC (peripheral clock cycle) × 32 cyc have elapsed.
Figure 17.11 HIFDREQ Timing (When DMD = 1 and DPOL = 1)
When the external DMAC supports intermittent operating mode (block transfer mode), efficient
data transfer can be implemented by using the HIFRAM consecutive access and bank functions.
Rev. 5.00 Mar. 15, 2007 Page 527 of 794
REJ09B0237-0500