SH7619 Datasheet, PDF (177/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
4
A3ROW1 0
R/W Number of Bits of Row Address for Area 3
3
A3ROW0 0
R/W Specify the number of bits of the row address for area 3.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
2

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
1
A3COL1 0
R/W Number of Bits of Column Address for Area 3
0
A3COL0 0
R/W Specify the number of bits of the column address for
area 3.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
7.4.5 Refresh Timer Control/Status Register (RTCSR)
RTCSR specifies various items about refresh for SDRAM.
When RTCSR is written to, the upper 16 bits of the write data must be H'A55A to cancel write
protection.
Bit
Bit Name
31 to 8 
Initial
Value
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 5.00 Mar. 15, 2007 Page 139 of 794
REJ09B0237-0500