SH7619 Datasheet, PDF (50/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 1 Overview
Classifi-
cation Abbr.
Ethernet TX_CLK
controller
TX_ER
MII_RXD3
to
MII_RXD0
RX_DV
RX_CLK
RX_ER
MDC
MDIO
WOL
LNKSTA
EXOUT
Direct
memory
access
controller
DREQ1,
DREQ0
DACK1,
DACK0
TEND1,
TEND0
Serial
TXD2 to
communi- TXD0
cation
interface
with FIFO
RXD2 to
RXD0
SCK2 to
SCK0
RTS1 and
RTS0
I/O Pin Name Description
Input Transmit
Clock
Timing reference input for the TX_EN, TX_ER, and MII_TXD3
to MII_TXD0 pins
Output Transmit Error Informs PHY LSI of an error during transmission.
Input Receive Data 4-bit receive data pins
Input Receive Data Indicates that valid receive data is on pins MII_RXD3 to
Valid
MII_RXD0.
Input Receive Clock Timing reference input for the RX_DV, RX_ER, and
MII_RXD3 to MII_RXD0 pins
Input Receive Error Pin for detection of an error during reception
Output Management Timing reference input for transfer information on the MDIO
Clock
pin
Input/ Management Bidirectional pin for management information transfer
output Data I/O
Output MAGIC
Packet
Receive
Indicates that a Magic Packet* has received.
Input Link Status Input pin for a link state from a PHY LSI.
Output General
Output
Output pin to external devices
Input DMA transfer Input pins for external DMA transfer request
request
Output DMA transfer Request receive output pins for external DMA transfer
request
request
receive
Output DMA transfer Output pins for DMA transfer end signal
end
Output Transmit Data Transmit data pins
Input Receive Data Receive data pins
Input/ Serial Clock
output
Output Transmit
Request
Clock input pins
Modem control pins. Supported only by SCIF0 and SCIF1.
Rev. 5.00 Mar. 15, 2007 Page 12 of 794
REJ09B0237-0500