SH7619 Datasheet, PDF (695/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
• Management signals
Signal Name
CO_MDI
CO_MDO
CO_MDCLK
CO_MDIO_DIR
Type Description
I
Management Data Input: Serial management data input.
O
Management Data Output: Serial management data output.
I
Management Clock: Serial management clock.
O
Management Data Direction: May be used to control output enabled
buffer for MDIO.
• General signals
Signal Name
CO_CLKIN
Type Description
I
Clock Input - PHY clock. Can be 25MHz either from mck of CPG
module or from CK_PHY pin.
22.12 Signals Relevant to PHY-IF
This PHY core has a part set up by the PHY-IF module.
(1) PHY address
The PHY address initialized by PHYIFADDR of PHY-IF, is same as the one that the ordinary
external PHY LSI has. It gives each PHY a unique address. This address is latched into an internal
register during Module reset and PHY power on reset. Originally, it enables a function to manage
each PHY via the unique address in a multi-PHY application.
About this PHY module, you can not connect multiple PHYs to the MII interface within the LSI.
But PHY address is also used to seed the scrambler, so that please accord the configuration of
PHYIFADDRR and the PHY address on the management interface.
(2) Operation mode
The co_st_mode of the PHYIFCR of PHY-IF controls the configuration of 10/100 digital block.
Rev. 5.00 Mar. 15, 2007 Page 657 of 794
REJ09B0237-0500