SH7619 Datasheet, PDF (170/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
SDRAM:
• CS3WCR
Initial
Bit
Bit Name Value R/W
31 to 15 
All 0 R
14
WTRP1 0
R/W
13
WTRP0 0
R/W
12

0
R
11
WTRCD1 0
R/W
10
WTRCD0 1
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Wait Cycle Number for Precharge Completion
Specify the number of minimum wait cycles inserted to
wait for the completion of precharge in the following
cases.
• From the start of auto-precharge to the issuing of the
ACTV command for the same bank.
• From the issuing of the PRE/PALL command to the
issuing of the ACTV command for the same bank.
• From the issuing of the PALL command during auto-
refreshing to the issuing of the REF command.
• From the issuing of the PALL command during self-
refreshing to the issuing of the SELF command.
00: 0 cycle (no wait cycle)
01: 1 cycle
10: 2 cycles
11: 3 cycles
Reserved
This bit is always read as 0. The write value should
always be 0.
Wait Cycle Number from ACTV Command to
READ(A)/WRIT(A) Command
Specify the number of minimum wait cycles from issuing
the ACTV command to issuing the READ(A)/WRIT(A)
command.
00: 0 cycle (no wait cycle)
01: 1 cycle
10: 2 cycles
11: 3 cycles
Rev. 5.00 Mar. 15, 2007 Page 132 of 794
REJ09B0237-0500