SH7619 Datasheet, PDF (558/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W
Description
0
BIF
0
R/W*¹ *² Bank Interrupt Request Flag
While this bit is 1, a bank interrupt request (HIFBI) is
issued to the on-chip CPU according to the setting of
the BIE bit.
In auto-increment mode (AI/AD bit in HIFMCR is 0),
this bit is automatically set to 1 when an external
device has completed access to the 32-bit data in the
end address of HIFRAM and the HIFCS pin has been
negated.
In auto-decrement mode (AI/AD bit in HIFMCR is 1),
this bit is automatically set to 1 when an external
device has completed access to the 32-bit data in the
start address of HIFRAM and the HIFCS pin has been
negated.
Though this bit can be cleared to 0 by the on-chip
CPU, it cannot be set to 1.
Make sure setting of this bit by HIFRAM access from
an external device and clearing of this bit by the on-
chip CPU do not conflict using software.
Notes: 1. This bit cannot be accessed by an external device. It can only be accessed by the on-
chip CPU.
2. Writing 1 to this bit by the on-chip CPU is ignored.
Rev. 5.00 Mar. 15, 2007 Page 520 of 794
REJ09B0237-0500