SH7619 Datasheet, PDF (662/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
Pin Name
Reference resistor
Test input/output
Abbreviation I/O
EXRES1
Input
TSTBUSA
I/O
Function
Connect to the ground through a resistor of
value 12.4Kohm, 1%.
I/O for test. Do not connect anything to this
pin.
22.3 Top Level Functional Architecture
Functionally, this PHY module can be divided into the following sections:
• 100Base-TX transmit and receive
• 10Base-T transmit and receive
• MII interface to the on-chip EtherC of this LSI
• Auto-negotiation to automatically determine the best speed and duplex possible
• Management Control to read status registers and write control register.
MII bus
MII
logic
10M Tx logic
100M Tx Logic
Transmit
100M Rx Logic
10M Transmitter
100M Transmitter
To magnetics
DSP system:
clock data
A/D
recovery
Equalizer
10M Rx Logic
100M PLL
Squelch and Filters
From magnetics
Receive
Auto-negotiation
10M PLL
Central Bias
SMI
Management
control
= Analog blocks
Figure 22.2 Architectural Overview
Rev. 5.00 Mar. 15, 2007 Page 624 of 794
REJ09B0237-0500