SH7619 Datasheet, PDF (317/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
12.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)
TRSCER specifies whether or not transmit and receive status information reported by bits in the
EtherC/E-DMAC status register is to be indicated in bits TFS26 to TFS0 and RFS26 to RFS0 in
the corresponding descriptor. Bits in this register correspond to bits 11 to 0 in the EtherC/E-
DMAC status register (EESR). When a bit is cleared to 0, the transmit status (bits 11 to 8 in
EESR) is indicated in bits TFS3 to TFS0 in the transmit descriptor, and the receive status (bits 7
to 0 in EESR) is indicated in bits RFS7 to RFS0 of the receive descriptor. When a bit is set to 1,
the occurrence of the corresponding interrupt is not indicated in the descriptor. After this LSI is
reset, all bits are cleared to 0.
Bit
Bit Name
31 to 12 
Initial
value
All 0
11
CNDCE 0
10
DLCCE
0
9
CDCE
0
8
TROCE
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W CND Bit Copy Directive
0: Indicates the CND bit state in bit TFS3 in the transmit
descriptor
1: Occurrence of the corresponding interrupt is not
indicated in bit TFS3 of the transmit descriptor
R/W DLC Bit Copy Directive
0: Indicates the DLC bit state in bit TFS2 of the transmit
descriptor
1: Occurrence of the corresponding interrupt is not
indicated in bit TFS2 of the transmit descriptor
R/W CD Bit Copy Directive
0: Indicates the CD bit state in bit TFS1 of the transmit
descriptor
1: Occurrence of the corresponding interrupt is not
indicated in bit TFS1 of the transmit descriptor
R/W TRO Bit Copy Directive
0: Indicates the TRO bit state in bit TFS0 of the receive
descriptor
1: Occurrence of the corresponding interrupt is not
indicated in bit TFS0 of the receive descriptor
Rev. 5.00 Mar. 15, 2007 Page 279 of 794
REJ09B0237-0500