SH7619 Datasheet, PDF (683/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
(1) 10M Transmit Data across the MII
The MAC controller (EtherC) drives the transmit data onto the CO_MII_TXD BUS. When the
controller (EtherC) has driven CO_TX_EN high to indicate valid data, the data is latched by the
MII block on the rising edge of CO_TX_CLK. The data is in the form of 4-bit wide 2.5 MHz data.
In order to comply with legacy 10Base-T MAC/Controllers, in Half-duplex mode the PHY loops
back the transmitted data, on the receive path. This does not confuse the MAC/Controller since the
CO_COL signal is not asserted during this time. The PHY also support the SQE (Heart beat)
signal.
(2) Manchester Encoding
The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial
NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces
a 20MHz clock. This is used to Manchester encode the NRZ data stream. When no data is being
transmitted (CO_TX_EN is low, the TX10M block outputs Normal Link Pulses (NLPs) to
maintain communications with the remote link partner.
Manchester encoded output
1
1
0
0
1
Data
Figure 22.9 Manchester Encoded Output
(3) 10M Transmit Drivers
The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered
before being driven out as a differential signal across the TXP and TXM outputs.
Rev. 5.00 Mar. 15, 2007 Page 645 of 794
REJ09B0237-0500