SH7619 Datasheet, PDF (342/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
12.4 Usage Notes
12.4.1 Usage Notes on SH-Ether EtherC/E-DMAC Status Register (EESR)
When the status bits in EESR of the on-chip E-DMAC of the SH-Ether chip are used as interrupt
sources, setting of the interrupt source may fail if software writes a 1 to the corresponding status
bit in EESR to clear the bit and this coincides with setting of the status interrupt source in EESR
by the EtherC or E-DMAC. Figure 12.8 shows an example of timing in the case where setting of
the interrupt source in EESR has failed.
(a) In this example, both the reception interrupt and transmission interrupt sources of EESR are
used. Firstly, reception interrupt source A from the EtherC or E-DMAC sets bit A in EESR
and an interrupt is generated.
(b) The interrupt handler writes 1 to bit A to clear it.
(c) If clearing of bit A by writing of a 1 and generation of the transmission-interrupt source B
signal by the EtherC or E-DMAC take place simultaneously, bit A will be cleared but the
status bit for transmission-interrupt source B in EESR might not be set.
(a)
Internal clock (Iφ)
Reception interrupt source A
generated by EtherC/E-DMAC
Transmission interrupt source B
generated by EtherC/E-DMAC
(b), (c)
(c)
Simultaneous clearing of the bit
by writing of a 1 and generation
of interrupt source B.
Bit A in EESR
Bit B in EESR
Write access to EESR
by software
Data to be written to EESR
Reception interrupt source A
is set in bit A of EESR.
Only bit A of EESR
is cleared by software.
Failure to generate transmission
H'00000001 _{interrupt source B due to}
non-setting of bit B.
Bit clearing
by writing a 1
: Expected operation
Figure 12.8 Timing of the Case where Setting of the Interrupt Source Bit in EESR by the E-
DMAC Fails
Rev. 5.00 Mar. 15, 2007 Page 304 of 794
REJ09B0237-0500