SH7619 Datasheet, PDF (432/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.8 Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the
CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive
bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.
Each channel has independent baud rate generator control, so different values can be set in three
channels.
The SCBRR setting is calculated as follows:
• Asynchronous mode:
N=
Pφ
× 10⁶ - 1
64 × 2^2n-1 × B
• Synchronous mode:
N=
Pφ
× 10⁶ - 1
8 × 2^2n-1 × B
B: Bit rate (bits/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
(The setting value should satisfy the electrical characteristics.)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 15.2.)
Rev. 5.00 Mar. 15, 2007 Page 394 of 794
REJ09B0237-0500