SH7619 Datasheet, PDF (825/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Index
Numerics
100Base-TX receive ............................... 641
100Base-TX transmit.............................. 638
100M phase lock loop (PLL) .................. 641
100M receive data across the MII........... 644
100M receive input................................. 641
100M transmit data across the MII ......... 638
100M transmit driver .............................. 640
10Base-T receive .................................... 646
10Base-T transmit................................... 644
10M receive data across the MII............. 646
10M receive input and squelch ............... 646
10M transmit data across the MII ........... 645
10M transmit drivers............................... 645
4B/5B encoding ...................................... 638
5B/4B decoding ...................................... 643
A
Access wait control................................. 154
Accessing MII registers .......................... 258
Address array............................................ 60
Address error exception handling ............. 73
Address error sources ............................... 73
Address multiplexing.............................. 159
Addressing modes..................................... 32
Alignment ............................................... 643
Arithmetic operation instructions ............. 45
Asynchronous mode ............................... 410
Auto-negotiation..................................... 648
Auto-negotiation disabling ..................... 650
Auto-refreshing....................................... 181
Auto-request mode ................................. 339
B
Bank active ............................................. 174
Basic timing ............................................ 149
Basic timing for I/O card interface.......... 195
Basic timing for memory card
interface .................................................. 193
Baud rate generator ................................. 473
Bit rate..................................................... 394
Boundary scan......................................... 620
Branch instructions ................................... 48
Burst mode.............................................. 350
Burst read................................................ 168
Burst write............................................... 172
Bus state controller (BSC) ...................... 107
Byte-selection SRAM interface .............. 186
C
Cache ........................................................ 53
Cache structure.......................................... 53
Carrier sense ........................................... 651
Cases when exceptions are accepted......... 78
Changing clock operating mode.............. 211
Changing division ratio........................... 211
Changing frequency ................................ 210
Changing multiplication ratio ................. 210
Clock operating modes ........................... 204
Clock pulse generator (CPG) .................. 201
Coherency of cache and external memory 59
Collision detect ....................................... 651
Compare match timer (CMT) ................. 363
Connection to PHY-LSI.......................... 263
Control registers........................................ 25
CPU........................................................... 23
Cycle-steal mode..................................... 348
Rev. 5.00 Mar. 15, 2007 Page 787 of 794
REJ09B0237-0500