SH7619 Datasheet, PDF (224/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
CKIO
Tp
Tpw
Trr
Trc
PALL
REF
Trc
Trr
Trc
REF
Trc Tmw Tnop
MRS
A25 to A0
A11*
CSn
RAS
CAS
RD/WR
DQMxx
D
Hi-Z
BS
Note: * Address pin to be connected to pin A10 of SDRAM.
Figure 7.27 Write Timing for SDRAM Mode Register (Based on JEDEC)
7.5.6 Byte-Selection SRAM Interface
The byte-selection SRAM interface is for access to SRAM which has a byte-selection pin (WEn
(BEn)). This interface is used to access to SRAM which has 16-bit data pins and upper and lower
byte selection pins, such as UB and LB.
When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the byte-
selection SRAM interface is the same as that for the normal space interface. While in read access
of a byte-selection SRAM interface, the byte-selection signal is output from the WEn (BEn) pin,
which is different from that for the normal space interface. The basic access timing is shown in
figure 7.28. In write access, data is written to the memory according to the timing of the byte-
selection pin (WEn (BEn)). For details, refer to the data sheet for the corresponding memory.
If the BAS bit in CSnWCR is set to 1, the WEn (BEn) pin and RD/WR pin timings change. The
basic access timing is shown in figure 7.29. In write access, data is written to the memory
according to the timing of the write enable pin (RD/WR). The data hold timing from RD/WR
negation to data write must be secured by setting bits HW1 to HW0 in CSnWCR. Figure 7.30
shows the access timing when a software wait is specified.
Rev. 5.00 Mar. 15, 2007 Page 186 of 794
REJ09B0237-0500