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SH7619 Datasheet, PDF (685/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series | |||
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Section 22 Ethernet Physical Layer Transceiver (PHY)
(4) Jabber detection
Jabber is a condition in which a station transmits for a period of time longer than the maximum
permissible packet length, usually due to a fault condition, that results in holding the CO_TX_EN
input for a long period. Special logic is used to detect the jabber state and abort the transmission to
the line, within 45ms. Once CO_TX_EN is deasserted, the logic resets the jabber condition.
Bit 1.1 indicates that a jabber condition was detected.
22.9 MAC Interface
The MII (Media Independent Interface) block is responsible for the communication with the
controller (EtherC). Special sets of hand-shake signals are used to indicate that valid
received/transmitted data is present on the 4 bit receive/transmit bus.
(1) The MII includes 16 interface signals:
⢠transmit data:
CO_MII_TXD[3:0]
⢠transmit strobe: CO_TX_EN
⢠transmit:
CO_TX_CLK
⢠transmit error:
CO_TX_ER
⢠receive data:
CO_MII_RXD[3:0]
⢠receive strobe:
CO_RX_DV
⢠receive clock:
CO_RX_CLK
⢠receive error:
CO_RX_ER
⢠collision indication: CO_COL
⢠carrier sense:
CO_CRS
On the transmit path, the PHY drives the transmit clock, CO_TX_CLK, to the controller (EtherC).
The controller (EtherC) synchronizes the transmit data to the rising edge of CO_TX_CLK. The
controller (EtherC) drives CO_TX_EN high to indicate valid transmit data. The controller
(EtherC) drives CO_TX_ER high when a transmit error is detected.
On the receive path, the PHY drives both the receive data, CO_RXD, and the CO_RX_CLK
signal. The controller (EtherC) clocks in the receive data on the rising edge of CO_RX_CLK
when the PHY drives CO_RX_DV high. The PHY drives CO_RX_ER high when a receive error
is detected.
Rev. 5.00 Mar. 15, 2007 Page 647 of 794
REJ09B0237-0500
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