SH7619 Datasheet, PDF (147/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

The block diagram of the BSC is shown in figure 7.1.
Section 7 Bus State Controller (BSC)
Bus
mastership
controller
CMNCR
Internal master
module
Internal slave
module
WAIT
CS0, CS3, CS4,
CS5B (CE1A),
CS6B (CE1B)
MD5
A25 to A0,
D31 to D0,
BS, RD/WR, RD,
WE3 (BE3, DQMUU),
WE2 (BE2, DQMUU),
WE1 (BE1, DQMUU,WE),
WE0 (BE0, DQMLL),
ICIOWR, ICIORD,
RAS, CAS,
CKE,
CE2A, CE2B
IOIS16
Wait
controller
Area
controller
Memory
controller
Refresh
controller
CS0WCR
CS6BWCR
RWTCNT
CS0BCR
CS6BBCR
SDCR
RTCSR
RTCNT
Comparator
RTCOR
[Legend]
CMNCR: Common control register
CSnWCR: CSn space wait control register (n = 0, 3, 4, 5B, 6B)
RWTCNT: Reset wait counter
CSnBCR: CSn space bus control register (n = 0, 3, 4, 5B, 6B)
SDCR: SDRAM control register
RTCSR: Refresh timer control/status register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
BSC
Figure 7.1 Block Diagram of BSC
Rev. 5.00 Mar. 15, 2007 Page 109 of 794
REJ09B0237-0500