SH7619 Datasheet, PDF (483/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
16.3.1 Mode Register (SIMDR)
SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode.
Initial
Bit
Bit Name Value R/W Description
15
TRMD1 1
R/W Transfer Mode 1, 0
14
TRMD0 0
R/W Select transfer mode. For details, see table 16.2.
00: Slave mode 1
01: Slave mode 2
10: Master mode 1
11: Master mode 2
13
SYNCAT 0
R/W SIOFSYNC Pin Valid Timing
Indicates the position of the SIOFSYNC signal to be
output as a synchronization pulse.
0: At the start-bit data of frame
1: At the last-bit data of slot
12
REDG
0
R/W Receive Data Sampling Edge
0: The SIOFRxD signal is sampled at the falling edge of
SIOFSCK (The SIOFTxD signal is transmitted at the
rising edge of SIOFSCK.)
1: The SIOFRxD signal is sampled at the rising edge of
SIOFSCK (The SIOFTxD signal is transmitted at the
falling edge of SIOFSCK.)
Note: This bit is valid only in master mode.
Rev. 5.00 Mar. 15, 2007 Page 445 of 794
REJ09B0237-0500