SH7619 Datasheet, PDF (609/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 19 I/O Ports
19.2 Port B
Port B of this LSI is an I/O port with 14 pins as shown in figure 19.2.
Port B
PB00 (input/output)/WAIT (input)
PB01 (input/output)/IOIS16 (input)
PB02 (input/output)/CKE (output)
PB03 (input/output)/CAS (output)
PB04 (input/output)/RAS (output)
PB05 (input/output)/WE2(BE2)/DQMUL/ICIORD (output)
PB06 (input/output)/WE3(BE3)/DQMUU/ICIOWR (output)
PB07 (input/output)/CE2B (output)
PB08 (input/output)/CS6B (output)/CE1B (output)
PB09 (input/output)/CE2A (output)
PB10 (input/output)/CS5B (output)/CE1A (output)
PB11 (input/output)/CS4 (output)
PB12 (input/output)/CS3 (output)
PB13 (input/output)/BS (output)
Figure 19.2 Port B
19.2.1 Register Description
Port B is a 14-bit I/O port that has a following register. For details on the address of this register
and the states of this register in each processing state, see section 24, List of Registers.
• Port B data register L (PBDRL)
19.2.2 Port B Data Register L (PBDRL)
PBDRL is a 16-bit readable/writable register which stores data for port B. Bits PB13DR to
PB0DR correspond to pins PB13 to PB00. (Description of multiplexed functions is omitted.)
When the pin function is general output port, if the value is written to PBDRL, the value is output
from the pin; if PBDRL is read, the value written to the register is directly read regardless of the
pin state.
Rev. 5.00 Mar. 15, 2007 Page 571 of 794
REJ09B0237-0500