SH7619 Datasheet, PDF (286/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 11 Ethernet Controller (EtherC)
11.3.10 Delayed Collision Detect Counter Register (CDCR)
CDCR is a 32-bit counter that indicates the number of delayed collisions on all lines from a start
of transmission. When the value in this register reaches H'FFFFFFFF, count-up is halted. The
counter value is cleared to 0 by a write to this register with any value.
Initial
Bit
Bit Name
Value
31 to 0 COSDC31 to All 0
COSDC0
R/W Description
R/W Delayed Collision Detect Count
These bits indicate the number of delayed collisions
on all lines from a start of transmission.
11.3.11 Lost Carrier Counter Register (LCCR)
LCCR is a 32-bit counter that indicates the number of times the carrier was lost during data
transmission. When the value in this register reaches H'FFFFFFFF, the count is halted. The
counter value is cleared to 0 by writing to this register with any value.
Bit
Bit Name
31 to 0 LCC31 to
LCC0
Initial
Value
All 0
R/W Description
R/W Lost Carrier Count
These bits indicate the number of times the carrier
was lost during data transmission.
11.3.12 Carrier Not Detect Counter Register (CNDCR)
CNDCR is a 32-bit counter that indicates the number of times the carrier could not be detected
while the preamble was being sent. When the value in this register reaches H'FFFFFFFF, the count
is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name
31 to 0 CNDC31 to
CNDC0
Initial
Value
All 0
R/W Description
R/W Carrier Not Detect Count
These bits indicate the number of times the carrier
was not detected.
Rev. 5.00 Mar. 15, 2007 Page 248 of 794
REJ09B0237-0500