SH7619 Datasheet, PDF (260/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 9 Watchdog Timer (WDT)
9.3.4 Using Interval Timer Mode
When operating in interval timer mode, interval timer interrupts are generated at every overflow of
the counter. This enables interrupts to be generated at set periods.
1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and
set the initial value of the counter in WTCNT.
2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.
3. When the WTCNT overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval
timer interrupt request is sent to the INTC. The WTCNT then resumes counting.
9.4 Usage Notes
Pay attention to the following points when using the WDT.
While using the WDT in interval mode, no overflow occurs by the H'00 immediately after writing
H'FF to WDTCNT. (IOVF in WTCSR is not set.)
The overflow occurs at the point when the count reaches H'00 after one cycle.
This phenomenon does not occur when the WDT is used in watchdog timer mode.
Rev. 5.00 Mar. 15, 2007 Page 222 of 794
REJ09B0237-0500