SH7619 Datasheet, PDF (246/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 8 Clock Pulse Generator (CPG)
Initial
Bit
Bit Name Value R/W
2
PFC2
0
R/W
1
PFC1
1
R/W
0
PFC0
1
R/W
Description
Peripheral Clock Frequency Division Ratio
Specify the division ratio of the peripheral clock
frequency with respect to the output frequency of PLL
circuit 1.
000: ×1
001: ×1/2
011: ×1/4
Other values: Setting prohibited
8.4.2 PHY Clock Frequency Control Register (MCLKCR)
MCLKCR is an 8-bit readable/writable register. This register must be written to in words. The
upper byte of the word data must be H'5A and the lower byte is the write data.
Initial
Bit
Bit Name Value R/W
7
FLSCS1 0
R/W
6
FLSCS0 1
R/W
5 to 3 
All 0
R
2
FLDIVS2 0
R/W
1
FLDIVS1 1
R/W
0
FLDIVS0 1
R/W
Description
Source Clock Select
Select the source clock.
00: PLL1 output clock
01: PLL1 output clock
10: Setting prohibited
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Divider Select
Set the division ratio of PLL1 output.
000: ×1
001: ×1/2
011: ×1/4
100: ×1/5
Other values: Setting prohibited
Rev. 5.00 Mar. 15, 2007 Page 208 of 794
REJ09B0237-0500