SH7619 Datasheet, PDF (566/836 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
Table 17.4 Consecutive Write Procedure to HIFRAM by External DMAC
External Device
No. CPU
DMAC
1
HIF initial setting
2
DMAC initial setting
3
Set HIFADR to
HIFRAM end address
−8
4
Select HIFDATA and
write dummy data (4
bytes) to HIFDATA
5
Set HIFRAM
consecutive write with
address increment in
HIFMCR
6
Select HIFDATA and →
write dummy data (4
bytes) to HIFDATA
HIF
→ HIF bank
interrupt
occurs
7
Activate DMAC ← Assert
HIFDREQ
8
Consecutive
data write to
bank 1 in
HIFRAM
9
Write to end → HIF bank
address of bank interrupt
1 in HIFRAM
occurs
completes and
operation halts
10
Re-activate
← Assert
DMAC
HIFDREQ
11
Consecutive
data write to
bank 0 in
HIFRAM
This LSI
CPU
HIF initial setting
→ HIFRAM bank switching
by HIF bank interrupt
handler (external device
accesses bank 1 and on-
chip CPU accesses
bank 0)
← Set DTRG bit to 1
→ HIFRAM bank switching
by HIF bank interrupt
handler (external device
accesses bank 0 and on-
chip CPU accesses
bank 1)
← Set DTRG bit to 1
Read data from bank 1 in
HIFRAM
Rev. 5.00 Mar. 15, 2007 Page 528 of 794
REJ09B0237-0500